Formal Veriication as a Design Tool -the Transponder Lock Example
نویسندگان
چکیده
We describe a methodology for the construction and validation of embedded systems with real-time constraints. Our methodology is based on object-oriented techniques and synchronous programming. This greatly eases the use of formal veriication to analyse the system, particularly to support design decisions. We use model checking to verify reactive behaviors and theorem proving to verify datatype behaviors. Our approach has been applied to develop industrial products. It is illustrated here with such a development, a transponder lock.
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